Engineering Research Paper: compared the latency delay difference between ASIC and FPGA.
Engineering Research Paper Set up CNN layer that includes ReLU function using C++. Verified testbench outcomes. Converted code description into accurate and optimized hardware models using Catapult HLS tool. Improved the hardware performance. Compared the latency delay difference between ASIC and FPGA. Converted Verilog code to Digital Logic Based Design using Genus tool.